System Synthesis for Networks of Programmable Blocks

The advent of sensor networks presents untapped opportunities for synthesis. We examine the problem of synthesis of behavioral specifications into networks of programmable sensor blocks. The particular behavioral specification we consider is an intuitive user-created network diagram of sensor blocks, each block having a pre-defined combinational or sequential behavior. We synthesize this specification to a new network that utilizes a minimum number of programmable blocks in place of the pre-defined blocks, thus reducing network size and hence network cost and power. We focus on the main task of this synthesis problem, namely partitioning pre-defined blocks onto a minimum number of programmable blocks, introducing the efficient but effective PareDown decomposition algorithm for the task. We describe the synthesis and simulation tools we developed. We provide results showing excellent network size reductions through such synthesis, and significant speedups of our algorithm over exhaustive search while obtaining near-optimal results for 15 real network designs as well as nearly 10,000 randomly generated designs.Comment: Submitted on behalf of EDAA (http://www.edaa.com/

A spontaneous mutation in MutL-Homolog 3 (HvMLH3) affects synapsis and crossover resolution in the barley desynaptic mutant des10

Although meiosis is evolutionarily conserved, many of the underlying mechanisms show species-specific differences. These are poorly understood in large genome plant species such as barley (Hordeum vulgare) where meiotic recombination is very heavily skewed to the ends of chromosomes. The characterization of mutant lines can help elucidate how recombination is controlled. We used a combination of genetic segregation analysis, cytogenetics, immunocytology and 3D imaging to genetically map and characterize the barley meiotic mutant DESYNAPTIC 10 (des10). We identified a spontaneous exonic deletion in the orthologue of MutL-Homolog 3 (HvMlh3) as the causal lesion. Compared with wild-type, des10 mutants exhibit reduced recombination and fewer chiasmata, resulting in the loss of obligate crossovers and leading to chromosome mis-segregation. Using 3D structured illumination microscopy (3D-SIM), we observed that normal synapsis progression was also disrupted in des10, a phenotype that was not evident with standard confocal microscopy and that has not been reported with Mlh3 knockout mutants in Arabidopsis. Our data provide new insights on the interplay between synapsis and recombination in barley and highlight the need for detailed studies of meiosis in nonmodel species. This study also confirms the importance of early stages of prophase I for the control of recombination in large genome cereals.Isabelle Colas, Malcolm Macaulay, James D. Higgins, Dylan Phillips, Abdellah Barakate ... Robbie Waugh ... et al

Tuning of Loop Cache Architectures to Programs in Embedded System Design

Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-based design, embedded system designers can now tune a loop cache architecture to best match a specific application. We developed an automated simulation environment to find the best loop cache architecture for a given application and technology. Using this environment, we show significant variation in the best architecture for different examples. The results support the need for future fast synthesis of tuned loop cache architectures

Power Estimator Development for Embedded System Memory Tuning

Memory accesses account for a large percentage of total power in microprocessor-based embedded systems. The increasing use of microprocessor cores and synthesis, rather than prefabricated microprocessor chips, creates the opportunity to tune a memory hierarchy to the one program that will execute in the embedded system. Such tuning requires fast and accurate estimation of the power and performance of different memory configurations. We describe a general three-step approach to developing such estimators, based on our experiences on several different projects. Each step is increasingly fast, using the previous step to gauge accuracy. The first step uses high-level functional simulation, the second step uses trace simulation, and the third step uses equations. A tool developer can follow these three steps to create a powerful environment for core users to support synthesis of the best memory hierarchy for a particular embedded system. The approach can be applied to components other than memory also